EPROM Data Encoding

The simplest way to encode the the video waveform would be to directly scale the video waveform to a number in the range 0 to 255 i.e. sync pulse at 0% -> EPROM code 0, black at 30% -> EPROM code 0.3*256=77, and peak white at 100% -> EPROM code 255. However, this poses two problems:-

1) The actual image data then lies in the range 77 to 255 i.e. 179 shades. This will be awkward to generate from a standard 256 grey-scale PC based image.
2) A seperate sync seperator circuit will be required for triggering an oscilloscope.

The solution to this is to use 7-bits for the actual picture data, and use the most significant data bit from the EPROM to signal whether the EPROM data is picture data or timing information. Thus the EPROM is encoded as :-

EPROM Code Decription Simplified Video Waveform [10K]
Decimal Hex
0 .. 127 0x00..0x7F Picture Information
128 0x80 (Not used)
129 0x81 Sync Pulse
130 0x82 Frame signal.
131 0x83 Frame signal and Sync Pulse
132 0x84 (Used as a reset pulse that will be dicussed later)
133..255 0x85..0xFF (Not used)

When the EPROM is outputting timing information we can still feed the LS 7 data bits to our video DAC, since these bits will only represent a <1% signal. The "Sync" signal is responsible for generating the first 30% of the signal with the DAC producing the remaining 70% of the signal.

The EPROM data can then be fed to the following simple circuit to generate the various waveforms required :-

Initial output circuit [6K] The "Frame Scan" signal is for feeding into the 'Y' amplifier of in oscilloscope in order to generate a frame scanning waveform. It will be somewhat non-linear but ought to be adequate for test purposes.

The "Frame Sync" is the "Frame Signal" of the previous diagram, intended to provide a trigger pulse for an oscilloscope for when checking out frame timebase circuitry.

The "Line Sync" isn't strictly only line sync pulses, it is actually the (inverse of) the "Sync Signal" of the previous diagram. However it is useful for triggering an oscilloscope for when checking out line timebase circuitry.

For simplicity, I've drawn the DAC as if it were a bunch of resistors (of un-equal values) operating as a potential divider. An additional resistor is connected from the "Line Sync" signal to the "Video Signal", which is intended to generate a 30% signal level when the "Line Sync" signal is at a logic '1'. The actual DAC and output circuitry is discuseed in the DAC section.

Next Page : EPROM Design


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27th July 2002