EPROM DESIGN

So, now to the generation of the EPROM data. The highest frequency component of something like test card 'C' is 3MHz, thus to reproduce this we will need a 6MHz data rate. The EPROM size will therefore need to be:-

EPROM SIZE = 405 lines *98.7uS/Line * 6bytes/uS
  = 239,841 Bytes => 256Kx8 EPROM (2 megabit) - a 27C2001 fits the bill.

This requires an 18-bit address counter (256K == 2^18).

For info : A glance in the Maplin electronics catalogue shows that a 4 megabit EPROM only cost 10% more than the 2 megabit EPROM, so you may wish to use the larger device. You will certainly need this if you wish to use this circuit to generate a 625 line signal. Or maybe you you could store two different test cards and switch between the two.

One potential problem is the EPROM access time, that is, the time between the input address being valid and the correct data being output from the EPROM. This could result in a lot of switching glitches which would be unacceptable. Therefor, a latch needs to be added to latch the data at the appropriate time.

The 74ACT374 or 74ACT574 8-bit latch devices are ideal for this job, latching data on the rising edge of a clock signal. If we arrange for the address counter to increment on the falling clock edge then we will have 1/2 a clock cycle for the EPROM data to settle.

Next Page : The Address Counter


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J.Evans 2002
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Last updated
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